patch-2.1.53 linux/include/asm-sparc64/sysio.h

• Lines: 136
• Date: Thu Sep 4 12:54:49 1997
• Orig file: v2.1.52/linux/include/asm-sparc64/sysio.h
• Orig date: Mon Aug 18 18:19:47 1997

diff -u --recursive --new-file v2.1.52/linux/include/asm-sparc64/sysio.h linux/include/asm-sparc64/sysio.h
@@ -1,4 +1,4 @@
-/* $Id: sysio.h,v 1.6 1997/08/15 06:44:53 davem Exp $
+/* $Id: sysio.h,v 1.7 1997/08/18 03:47:26 davem Exp $
  * sysio.h: UltraSparc sun5 specific SBUS definitions.
  *
  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -280,7 +280,7 @@
 #define SYSIO_SBAFSR_MID	0x000003e000000000 /* MID causing the error        */
 #define SYSIO_SBAFSR_RESV3	0x0000001fffffffff /* Reserved                     */
 
-/* SYSIO SBUS Slot Configuration Register */
+/* SYSIO SBUS Slot Configuration Register(s) */
 #define SYSIO_SBSCFG_RESV1	0xfffffffff8000000 /* Reserved                     */
 #define SYSIO_SBSCFG_SADDR	0x0000000007ff0000 /* Segment Address (PA[40:30])  */
 #define SYSIO_SBSCFG_CP		0x0000000000008000 /* Bypasses are cacheable       */
@@ -326,14 +326,115 @@
 /* SYSIO Interrupt Retry Timer register. */
 #define SYSIO_IRETRY_LIMIT	0x000000ff	/* The retry interval.		   */
 
-/* SYSIO Interrupt State registers. XXX fields to be documented later */
+/* SYSIO Interrupt State registers. */
+#define SYSIO_ISTATE_IDLE	0x0 /* No interrupt received or pending */
+#define SYSIO_ISTATE_TRANSMIT	0x1 /* Received, but IRQ not dispatched */
+#define SYSIO_ISTATE_ILLEGAL	0x2 /* Impossible state                 */
+#define SYSIO_ISTATE_PENDING	0x3 /* Received and dispatched          */
+
+/* Two ways to get at the right bits, your choice... note that level
+ * zero is illegal.  For slots 0 --> 3 the formula for the bit range
+ * in the register is:
+ *
+ *	LSB	((SBUS_SLOT X 16) + (SBUS_LEVEL X 2))
+ *	MSB	((SBUS_SLOT X 16) + (SBUS_LEVEL X 2)) + 1
+ *
+ * Thus the following macro.
+ */
+#define SYSIO_SBUS_ISTATE(regval, slot, level)	\
+	(((regval) >> (((slot) * 16) + ((level) * 2))) & 0x3)
 
-/* SYSIO Counter register. XXX fields to be documented later */
+#define SYSIO_SBUS_ISTATE_S0L1	0x000000000000000c /* Slot 0, level 1 */
+#define SYSIO_SBUS_ISTATE_S0L2	0x0000000000000030 /* Slot 0, level 2 */
+#define SYSIO_SBUS_ISTATE_S0L3	0x00000000000000c0 /* Slot 0, level 3 */
+#define SYSIO_SBUS_ISTATE_S0L4	0x0000000000000300 /* Slot 0, level 4 */
+#define SYSIO_SBUS_ISTATE_S0L5	0x0000000000000c00 /* Slot 0, level 5 */
+#define SYSIO_SBUS_ISTATE_S0L6	0x0000000000003000 /* Slot 0, level 6 */
+#define SYSIO_SBUS_ISTATE_S0L7	0x000000000000c000 /* Slot 0, level 7 */
+#define SYSIO_SBUS_ISTATE_S1L1	0x00000000000c0000 /* Slot 1, level 1 */
+#define SYSIO_SBUS_ISTATE_S1L2	0x0000000000300000 /* Slot 1, level 2 */
+#define SYSIO_SBUS_ISTATE_S1L3	0x0000000000c00000 /* Slot 1, level 3 */
+#define SYSIO_SBUS_ISTATE_S1L4	0x0000000003000000 /* Slot 1, level 4 */
+#define SYSIO_SBUS_ISTATE_S1L5	0x000000000c000000 /* Slot 1, level 5 */
+#define SYSIO_SBUS_ISTATE_S1L6	0x0000000030000000 /* Slot 1, level 6 */
+#define SYSIO_SBUS_ISTATE_S1L7	0x00000000c0000000 /* Slot 1, level 7 */
+#define SYSIO_SBUS_ISTATE_S2L1	0x0000000c00000000 /* Slot 2, level 1 */
+#define SYSIO_SBUS_ISTATE_S2L2	0x0000003000000000 /* Slot 2, level 2 */
+#define SYSIO_SBUS_ISTATE_S2L3	0x000000c000000000 /* Slot 2, level 3 */
+#define SYSIO_SBUS_ISTATE_S2L4	0x0000030000000000 /* Slot 2, level 4 */
+#define SYSIO_SBUS_ISTATE_S2L5	0x00000c0000000000 /* Slot 2, level 5 */
+#define SYSIO_SBUS_ISTATE_S2L6	0x0000300000000000 /* Slot 2, level 6 */
+#define SYSIO_SBUS_ISTATE_S2L7	0x0000c00000000000 /* Slot 2, level 7 */
+#define SYSIO_SBUS_ISTATE_S3L1	0x000c000000000000 /* Slot 3, level 1 */
+#define SYSIO_SBUS_ISTATE_S3L2	0x0030000000000000 /* Slot 3, level 2 */
+#define SYSIO_SBUS_ISTATE_S3L3	0x00c0000000000000 /* Slot 3, level 3 */
+#define SYSIO_SBUS_ISTATE_S3L4	0x0300000000000000 /* Slot 3, level 4 */
+#define SYSIO_SBUS_ISTATE_S3L5	0x0c00000000000000 /* Slot 3, level 5 */
+#define SYSIO_SBUS_ISTATE_S3L6	0x3000000000000000 /* Slot 3, level 6 */
+#define SYSIO_SBUS_ISTATE_S3L7	0xc000000000000000 /* Slot 3, level 7 */
 
-/* SYSIO Limit register. XXX fields to be documented later */
+/* For OBIO devices things are a bit different, you just have to know what
+ * you are looking for.
+ */
+#define SYSIO_OBIO_ISTATE_SCSI	0x0000000000000003 /* Scsi		*/
+#define SYSIO_OBIO_ISTATE_ETH	0x000000000000000c /* Ethernet		*/
+#define SYSIO_OBIO_ISTATE_PP	0x0000000000000030 /* Parallel Port	*/
+#define SYSIO_OBIO_ISTATE_AUDIO	0x00000000000000c0 /* Sun Audio		*/
+#define SYSIO_OBIO_ISTATE_PFAIL	0x0000000000000300 /* Power Fail	*/
+#define SYSIO_OBIO_ISTATE_KBMS	0x0000000000000c00 /* kbd/mouse/serial	*/
+#define SYSIO_OBIO_ISTATE_FLPY	0x0000000000003000 /* Floppy Controller	*/
+#define SYSIO_OBIO_ISTATE_SPHW	0x000000000000c000 /* Spare HW		*/
+#define SYSIO_OBIO_ISTATE_KBD	0x0000000000030000 /* Keyboard		*/
+#define SYSIO_OBIO_ISTATE_MS	0x00000000000c0000 /* Mouse		*/
+#define SYSIO_OBIO_ISTATE_SER	0x0000000000300000 /* Serial		*/
+#define SYSIO_OBIO_ISTATE_TIM0	0x0000000000c00000 /* Timer 0		*/
+#define SYSIO_OBIO_ISTATE_TIM1	0x0000000003000000 /* Timer 1		*/
+#define SYSIO_OBIO_ISTATE_UE	0x000000000c000000 /* Uncorrectable Err	*/
+#define SYSIO_OBIO_ISTATE_CE	0x0000000030000000 /* Correctable Err	*/
+#define SYSIO_OBIO_ISTATE_SERR	0x00000000c0000000 /* SBUS Err		*/
+#define SYSIO_OBIO_ISTATE_PMGMT	0x0000000300000000 /* Power Management	*/
+#define SYSIO_OBIO_ISTATE_RSVI	0x0000000400000000 /* Reserved Int	*/
+#define SYSIO_OBIO_ISTATE_EUPA	0x0000000800000000 /* Expansion UPA (creator) */
+#define SYSIO_OBIO_ISTATE_RESV	0xfffffff000000000 /* Reserved...	*/
 
-/* SYSIO Performance Monitor Control register. XXX fields to be documented later */
+/* SYSIO Counter and Limit registers are documented in timer.h as these
+ * are generic SUN4U things.
+ */
 
-/* SYSIO Performance Monitor Counter register. XXX fields to be documented later */
+/* SYSIO Performance Monitor Control register. */
+#define SYSIO_PCNTRL_CLR1	0x0000000000008000 /* Clear SEL1 counter              */
+#define SYSIO_PCNTRL_SEL1_SDR	0x0000000000000000 /* SEL1: Streaming DVMA reads      */
+#define SYSIO_PCNTRL_SEL1_SDW	0x0000000000000100 /* SEL1: Streaming DVMA writes     */
+#define SYSIO_PCNTRL_SEL1_CDR	0x0000000000000200 /* SEL1: Consistent DVMA reads     */
+#define SYSIO_PCNTRL_SEL1_CDW	0x0000000000000300 /* SEL1: Consistent DVMA writes    */
+#define SYSIO_PCNTRL_SEL1_TMISS	0x0000000000000400 /* SEL1: IOMMU TLB misses          */
+#define SYSIO_PCNTRL_SEL1_SMISS	0x0000000000000500 /* SEL1: Streaming Buffer misses   */
+#define SYSIO_PCNTRL_SEL1_SDC	0x0000000000000600 /* SEL1: SBUS dvma cycles          */
+#define SYSIO_PCNTRL_SEL1_DB	0x0000000000000700 /* SEL1: DVMA bytes transferred    */
+#define SYSIO_PCNTRL_SEL1_IRQ	0x0000000000000800 /* SEL1: Interrupts                */
+#define SYSIO_PCNTRL_SEL1_UIN	0x0000000000000900 /* SEL1: UPA IRQ NACK's            */
+#define SYSIO_PCNTRL_SEL1_PRD	0x0000000000000a00 /* SEL1: PIO reads                 */
+#define SYSIO_PCNTRL_SEL1_PWR	0x0000000000000b00 /* SEL1: PIO writes                */
+#define SYSIO_PCNTRL_SEL1_SRR	0x0000000000000c00 /* SEL1: SBUS reruns               */
+#define SYSIO_PCNTRL_SEL1_SPIO	0x0000000000000d00 /* SEL1: SYSIO PIO cycles          */
+#define SYSIO_PCNTRL_CLR0	0x0000000000000080 /* Clear SEL0 counter              */
+#define SYSIO_PCNTRL_SEL0_SDR	0x0000000000000000 /* SEL0: Streaming DVMA reads      */
+#define SYSIO_PCNTRL_SEL0_SDW	0x0000000000000001 /* SEL0: Streaming DVMA writes     */
+#define SYSIO_PCNTRL_SEL0_CDR	0x0000000000000002 /* SEL0: Consistent DVMA reads     */
+#define SYSIO_PCNTRL_SEL0_CDW	0x0000000000000003 /* SEL0: Consistent DVMA writes    */
+#define SYSIO_PCNTRL_SEL0_TMISS	0x0000000000000004 /* SEL0: IOMMU TLB misses          */
+#define SYSIO_PCNTRL_SEL0_SMISS	0x0000000000000005 /* SEL0: Streaming Buffer misses   */
+#define SYSIO_PCNTRL_SEL0_SDC	0x0000000000000006 /* SEL0: SBUS dvma cycles          */
+#define SYSIO_PCNTRL_SEL0_DB	0x0000000000000007 /* SEL0: DVMA bytes transferred    */
+#define SYSIO_PCNTRL_SEL0_IRQ	0x0000000000000008 /* SEL0: Interrupts                */
+#define SYSIO_PCNTRL_SEL0_UIN	0x0000000000000009 /* SEL0: UPA IRQ NACK's            */
+#define SYSIO_PCNTRL_SEL0_PRD	0x000000000000000a /* SEL0: PIO reads                 */
+#define SYSIO_PCNTRL_SEL0_PWR	0x000000000000000b /* SEL0: PIO writes                */
+#define SYSIO_PCNTRL_SEL0_SRR	0x000000000000000c /* SEL0: SBUS reruns               */
+#define SYSIO_PCNTRL_SEL0_SPIO	0x000000000000000d /* SEL0: SYSIO PIO cycles          */
+
+/* SYSIO Performance Monitor Counter register. */
+#define SYSIO_PCOUNT_CNT0	0xffffffff00000000 /* Counter zero  */
+#define SYSIO_PCOUNT_CNT1	0x00000000ffffffff /* Counter one  */
 
 #endif /* !(__SPARC64_SYSIO_H) */