patch-2.1.93 linux/arch/i386/kernel/smp.c

• Lines: 91
• Date: Sun Apr 5 12:08:41 1998
• Orig file: v2.1.92/linux/arch/i386/kernel/smp.c
• Orig date: Tue Mar 17 22:18:14 1998

diff -u --recursive --new-file v2.1.92/linux/arch/i386/kernel/smp.c linux/arch/i386/kernel/smp.c
@@ -128,9 +128,6 @@
 static int smp_activated = 0;				/* Tripped once we need to start cross invalidating 	*/
 int apic_version[NR_CPUS];				/* APIC version number					*/
 static volatile int smp_commenced=0;			/* Tripped when we start scheduling 		    	*/
-unsigned long apic_addr = 0xFEE00000;			/* Address of APIC (defaults to 0xFEE00000)		*/
-unsigned long nlong = 0;				/* dummy used for apic_reg address + 0x20		*/
-unsigned char *apic_reg=((unsigned char *)(&nlong))-0x20;/* Later set to the ioremap() of the APIC 		*/
 unsigned long apic_retval;				/* Just debugging the assembler.. 			*/
 
 static volatile unsigned char smp_cpu_in_msg[NR_CPUS];	/* True if this processor is sending an IPI		*/
@@ -150,6 +147,7 @@
 int mp_bus_id_to_type [MAX_MP_BUSSES] = { -1, };
 extern int mp_irq_entries;
 extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
+extern int mpc_default_type;
 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { -1, };
 int mp_current_pci_id = 0;
 
@@ -272,8 +270,9 @@
 
 	printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
 
-	/* set the local APIC address */
-	apic_addr = (unsigned long)phys_to_virt((unsigned long)mpc->mpc_lapic);
+	/* check the local APIC address */
+	if ((char *)phys_to_virt((unsigned long)mpc->mpc_lapic) != APIC_BASE)
+		panic("unexpected APIC address");
 
 	/*
 	 *	Now process the configuration blocks.
@@ -454,7 +453,7 @@
 					 */
 			
 					cfg=pg0[0];
-					pg0[0] = (apic_addr | 7);
+					pg0[0] = ((unsigned long)APIC_BASE | 7);
 					local_flush_tlb();
 
 					boot_cpu_id = GET_APIC_ID(*((volatile unsigned long *) APIC_ID));
@@ -477,6 +476,14 @@
 					cpu_present_map=3;
 					num_processors=2;
 					printk("I/O APIC at 0xFEC00000.\n");
+
+					/*
+					 * Save the default type number, we
+					 * need it later to set the IO-APIC
+					 * up properly:
+					 */
+					mpc_default_type = mpf->mpf_feature1;
+
 					printk("Bus #0 is ");
 				}
 				switch(mpf->mpf_feature1)
@@ -525,11 +532,6 @@
 				if(mpf->mpf_physptr)
 					smp_read_mpc((void *)mpf->mpf_physptr);
 
-				/*
-				 *	Now that the boot CPU id is known,
-				 *	set some other information about it.
-				 */
-				nlong = boot_cpu_id<<24;	/* Dummy 'self' for bootup */
 				__cpu_logical_map[0] = boot_cpu_id;
 				global_irq_holder = boot_cpu_id;
 				current->processor = boot_cpu_id;
@@ -951,15 +953,6 @@
 		printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
 	}
 
-	/*
-	 *	Map the local APIC into kernel space
-	 */
-
-	apic_reg = ioremap(apic_addr,4096);
-
-	if(apic_reg == NULL)
-		panic("Unable to map local apic.");
-
 #ifdef SMP_DEBUG
 	{
 		int reg;
@@ -1497,7 +1490,7 @@
 /*
  * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
  * per second. We assume that the caller has already set up the local
- * APIC at apic_addr.
+ * APIC.
  *
  * The APIC timer is not exactly sync with the external timer chip, it
  * closely follows bus clocks.