patch-2.4.19 linux-2.4.19/include/asm-mips/asm.h

• Lines: 356
• Date: Fri Aug 2 17:39:45 2002
• Orig file: linux-2.4.18/include/asm-mips/asm.h
• Orig date: Sun Sep 9 10:43:01 2001

diff -urN linux-2.4.18/include/asm-mips/asm.h linux-2.4.19/include/asm-mips/asm.h
@@ -1,11 +1,10 @@
 /*
- * include/asm-mips/asm.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2002  Maciej W. Rozycki
  *
  * Some useful macros for MIPS assembler code
  *
@@ -16,6 +15,7 @@
 #ifndef	__ASM_ASM_H
 #define	__ASM_ASM_H
 
+#include <linux/config.h>
 #include <asm/sgidefs.h>
 
 #ifndef CAT
@@ -28,16 +28,6 @@
 #endif
 
 /*
- * Macros to handle different pointer/register sizes for 32/64-bit code
- *
- * 64 bit address space isn't used yet, so we may use the R3000 32 bit
- * defines for now.
- */
-#define PTR	.word
-#define PTRSIZE	4
-#define PTRLOG	2
-
-/*
  * PIC specific declarations
  * Not used for the kernel but here seems to be the right place.
  */
@@ -124,20 +114,20 @@
 		TEXT(string)
 
 #define	TEXT(msg)                                       \
-		.data;                                  \
+		.pushsection .data;			\
 8:		.asciiz	msg;                            \
-		.previous;
+		.popsection;
 
 /*
  * Build text tables
  */
 #define TTABLE(string)                                  \
-		.text;                                  \
+		.pushsection .text;			\
 		.word	1f;                             \
-		.previous;                              \
-		.data;                                  \
-1:		.asciz	string;                         \
-		.previous
+		.popsection				\
+		.pushsection .data;			\
+1:		.asciiz	string;                         \
+		.popsection
 
 /*
  * MIPS IV pref instruction.
@@ -146,15 +136,25 @@
  * MIPS IV implementations are free to treat this as a nop.  The R5000
  * is one of them.  So we should have an option not to use this instruction.
  */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#if CONFIG_CPU_HAS_PREFETCH
+
 #define PREF(hint,addr)                                 \
-		pref	hint,addr
+		.set	push;				\
+		.set	mips4;				\
+		pref	hint,addr;			\
+		.set	pop
+
 #define PREFX(hint,addr)                                \
-		prefx	hint,addr
+		.set	push;				\
+		.set	mips4;				\
+		prefx	hint,addr;			\
+		.set	pop
+
 #else
-#define PREF
-#define PREFX
+
+#define PREF(hint,addr)
+#define PREFX(hint,addr)
+
 #endif
 
 /*
@@ -163,14 +163,14 @@
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
 #define MOVN(rd,rs,rt)                                  \
 		.set	push;				\
-		.set	noreorder;			\
+		.set	reorder;			\
 		beqz	rt,9f;                          \
 		move	rd,rs;                          \
 		.set	pop;				\
 9:
 #define MOVZ(rd,rs,rt)                                  \
 		.set	push;				\
-		.set	noreorder;			\
+		.set	reorder;			\
 		bnez	rt,9f;                          \
 		move	rd,rt;                          \
 		.set	pop;				\
@@ -181,24 +181,24 @@
 		.set	push;				\
 		.set	noreorder;			\
 		bnezl	rt,9f;                          \
-		move	rd,rs;                          \
+		 move	rd,rs;                          \
 		.set	pop;				\
 9:
 #define MOVZ(rd,rs,rt)                                  \
 		.set	push;				\
 		.set	noreorder;			\
 		beqzl	rt,9f;                          \
-		movz	rd,rs;                          \
+		 move	rd,rs;                          \
 		.set	pop;				\
 9:
 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS64)
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
 #define MOVN(rd,rs,rt)                                  \
 		movn	rd,rs,rt
 #define MOVZ(rd,rs,rt)                                  \
 		movz	rd,rs,rt
-#endif /* MIPS IV, MIPS V or MIPS64 */
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
 
 /*
  * Stack alignment
@@ -215,6 +215,10 @@
 #endif
 
 /*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
  * Size of a register
  */
 #ifdef __mips64
@@ -229,59 +233,54 @@
  */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS32)
-#define REG_S sw
-#define REG_L lw
-#define PTR_SUBU subu
-#define PTR_ADDU addu
+#define REG_S		sw
+#define REG_L		lw
+#define REG_SUBU	subu
+#define REG_ADDU	addu
 #endif
 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define REG_S sd
-#define REG_L ld
-/* We still live in a 32 bit address space ...  */
-#define PTR_SUBU subu
-#define PTR_ADDU addu
+#define REG_S		sd
+#define REG_L		ld
+#define REG_SUBU	dsubu
+#define REG_ADDU	daddu
 #endif
 
 /*
  * How to add/sub/load/store/shift C int variables.
  */
 #if (_MIPS_SZINT == 32)
-#define INT_ADD	add
-#define INT_ADDI	addi
+#define INT_ADD		add
 #define INT_ADDU	addu
+#define INT_ADDI	addi
 #define INT_ADDIU	addiu
-#define INT_SUB	add
-#define INT_SUBI	subi
+#define INT_SUB		sub
 #define INT_SUBU	subu
-#define INT_SUBIU	subu
 #define INT_L		lw
 #define INT_S		sw
-#define LONG_SLL	sll
-#define LONG_SLLV	sllv
-#define LONG_SRL	srl
-#define LONG_SRLV	srlv
-#define LONG_SRA	sra
-#define LONG_SRAV	srav
+#define INT_SLL		sll
+#define INT_SLLV	sllv
+#define INT_SRL		srl
+#define INT_SRLV	srlv
+#define INT_SRA		sra
+#define INT_SRAV	srav
 #endif
 
 #if (_MIPS_SZINT == 64)
-#define INT_ADD	dadd
-#define INT_ADDI	daddi
+#define INT_ADD		dadd
 #define INT_ADDU	daddu
+#define INT_ADDI	daddi
 #define INT_ADDIU	daddiu
-#define INT_SUB	dadd
-#define INT_SUBI	dsubi
+#define INT_SUB		dsub
 #define INT_SUBU	dsubu
-#define INT_SUBIU	dsubu
 #define INT_L		ld
 #define INT_S		sd
-#define LONG_SLL	dsll
-#define LONG_SLLV	dsllv
-#define LONG_SRL	dsrl
-#define LONG_SRLV	dsrlv
-#define LONG_SRA	dsra
-#define LONG_SRAV	dsrav
+#define INT_SLL		dsll
+#define INT_SLLV	dsllv
+#define INT_SRL		dsrl
+#define INT_SRLV	dsrlv
+#define INT_SRA		dsra
+#define INT_SRAV	dsrav
 #endif
 
 /*
@@ -289,13 +288,11 @@
  */
 #if (_MIPS_SZLONG == 32)
 #define LONG_ADD	add
-#define LONG_ADDI	addi
 #define LONG_ADDU	addu
+#define LONG_ADDI	addi
 #define LONG_ADDIU	addiu
-#define LONG_SUB	add
-#define LONG_SUBI	subi
+#define LONG_SUB	sub
 #define LONG_SUBU	subu
-#define LONG_SUBIU	subu
 #define LONG_L		lw
 #define LONG_S		sw
 #define LONG_SLL	sll
@@ -308,13 +305,11 @@
 
 #if (_MIPS_SZLONG == 64)
 #define LONG_ADD	dadd
-#define LONG_ADDI	daddi
 #define LONG_ADDU	daddu
+#define LONG_ADDI	daddi
 #define LONG_ADDIU	daddiu
-#define LONG_SUB	dadd
-#define LONG_SUBI	dsubi
+#define LONG_SUB	dsub
 #define LONG_SUBU	dsubu
-#define LONG_SUBIU	dsubu
 #define LONG_L		ld
 #define LONG_S		sd
 #define LONG_SLL	dsll
@@ -328,17 +323,16 @@
 /*
  * How to add/sub/load/store/shift pointers.
  */
-#if (_MIPS_SZLONG == 32)
-#define PTR_ADD	add
-#define PTR_ADDI	addi
+#if (_MIPS_SZPTR == 32)
+#define PTR_ADD		add
 #define PTR_ADDU	addu
+#define PTR_ADDI	addi
 #define PTR_ADDIU	addiu
-#define PTR_SUB		add
-#define PTR_SUBI	subi
+#define PTR_SUB		sub
 #define PTR_SUBU	subu
-#define PTR_SUBIU	subu
 #define PTR_L		lw
 #define PTR_S		sw
+#define PTR_LA		la
 #define PTR_SLL		sll
 #define PTR_SLLV	sllv
 #define PTR_SRL		srl
@@ -347,19 +341,22 @@
 #define PTR_SRAV	srav
 
 #define PTR_SCALESHIFT	2
+
+#define PTR		.word
+#define PTRSIZE		4
+#define PTRLOG		2
 #endif
 
-#if (_MIPS_SZLONG == 64)
-#define PTR_ADD	dadd
-#define PTR_ADDI	daddi
+#if (_MIPS_SZPTR == 64)
+#define PTR_ADD		dadd
 #define PTR_ADDU	daddu
+#define PTR_ADDI	daddi
 #define PTR_ADDIU	daddiu
-#define PTR_SUB		dadd
-#define PTR_SUBI	dsubi
+#define PTR_SUB		dsub
 #define PTR_SUBU	dsubu
-#define PTR_SUBIU	dsubu
 #define PTR_L		ld
 #define PTR_S		sd
+#define PTR_LA		dla
 #define PTR_SLL		dsll
 #define PTR_SLLV	dsllv
 #define PTR_SRL		dsrl
@@ -368,6 +365,10 @@
 #define PTR_SRAV	dsrav
 
 #define PTR_SCALESHIFT	3
+
+#define PTR		.dword
+#define PTRSIZE		8
+#define PTRLOG		3
 #endif
 
 /*
@@ -375,13 +376,15 @@
  */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS32)
-#define MFC0	mfc0
-#define MTC0	mtc0
+#define MFC0		mfc0
+#define MTC0		mtc0
 #endif
 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MFC0	dmfc0
-#define MTC0	dmtc0
+#define MFC0		dmfc0
+#define MTC0		dmtc0
 #endif
 
+#define SSNOP		sll zero,zero,1
+
 #endif /* __ASM_ASM_H */