patch-2.4.22 linux-2.4.22/include/asm-ia64/sn/pci/pci_defs.h

• Lines: 138
• Date: 2003-08-25 04:44:43.000000000 -0700
• Orig file: linux-2.4.21/include/asm-ia64/sn/pci/pci_defs.h
• Orig date: 2003-06-13 07:51:38.000000000 -0700

diff -urN linux-2.4.21/include/asm-ia64/sn/pci/pci_defs.h linux-2.4.22/include/asm-ia64/sn/pci/pci_defs.h
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1992-1997,2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCI_DEFS_H
 #define _ASM_SN_PCI_PCI_DEFS_H
@@ -321,6 +321,112 @@
 
 #ifndef __ASSEMBLY__
 
+#ifdef LITTLE_ENDIAN
+
+/*
+ * PCI config space definition
+ */
+typedef volatile struct pci_cfg_s {
+	uint16_t	vendor_id;
+	uint16_t	dev_id;
+	uint16_t	cmd;
+	uint16_t	status;
+	uchar_t		rev;
+        uchar_t         prog_if;
+	uchar_t		sub_class;
+	uchar_t		class;
+	uchar_t		line_size;
+	uchar_t		lt;
+	uchar_t		hdr_type;
+	uchar_t		bist;
+	uint32_t	bar[6];
+	uint32_t	cardbus;
+	uint16_t	subsys_vendor_id;
+	uint16_t	subsys_dev_id;
+	uint32_t	exp_rom;
+	uint32_t	res[2];
+	uchar_t		int_line;
+	uchar_t		int_pin;
+	uchar_t		min_gnt;
+	uchar_t		max_lat;
+} pci_cfg_t;
+
+/*
+ * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs)
+ */
+typedef volatile struct pci_cfg1_s {
+	uint16_t	vendor_id;
+	uint16_t	dev_id;
+	uint16_t	cmd;
+	uint16_t	status;
+	uchar_t		rev;
+	uchar_t		prog_if;
+	uchar_t		sub_class;
+	uchar_t		class;
+	uchar_t		line_size;
+	uchar_t		lt;
+	uchar_t		hdr_type;
+	uchar_t		bist;
+	uint32_t	bar[2];
+	uchar_t		pri_bus_num;
+	uchar_t		snd_bus_num;
+	uchar_t		sub_bus_num;
+	uchar_t		slt;
+	uchar_t		io_base;
+	uchar_t		io_limit;
+	uint16_t	snd_status;
+	uint16_t	mem_base;
+	uint16_t	mem_limit;
+	uint16_t	pmem_base;
+	uint16_t	pmem_limit;
+	uint32_t	pmem_base_upper;
+	uint32_t	pmem_limit_upper;
+	uint16_t	io_base_upper;
+	uint16_t	io_limit_upper;
+	uint32_t	res;
+	uint32_t	exp_rom;
+	uchar_t		int_line;
+	uchar_t		int_pin;
+	uint16_t	ppb_control;
+
+} pci_cfg1_t;
+
+/*
+ * PCI-X Capability
+ */
+typedef volatile struct cap_pcix_cmd_reg_s {
+	uint16_t	data_parity_enable:	1,
+			enable_relaxed_order:	1,
+			max_mem_read_cnt:	2,
+			max_split:		3,
+			reserved1:		9;
+} cap_pcix_cmd_reg_t;
+
+typedef volatile struct cap_pcix_stat_reg_s {
+	uint32_t	func_num:		3,
+			dev_num:		5,
+			bus_num:		8,
+			bit64_device:		1,
+			mhz133_capable:		1,
+			split_complt_discard:	1,
+			unexpect_split_complt:	1,
+			device_complex:		1,
+			max_mem_read_cnt:	2,
+			max_out_split:		3,
+			max_cum_read:		3,
+			split_complt_err:	1,
+			reserved1:		2;
+} cap_pcix_stat_reg_t;
+
+typedef volatile struct cap_pcix_type0_s {
+	uchar_t			pcix_cap_id;
+	uchar_t			pcix_cap_nxt;
+	cap_pcix_cmd_reg_t	pcix_type0_command;
+	cap_pcix_stat_reg_t	pcix_type0_status;
+} cap_pcix_type0_t;
+
+#else
+
 /*
  * PCI config space definition
  */
@@ -388,6 +494,8 @@
 	uchar_t		int_line;
 } pci_cfg1_t;
 
+
+
 /*
  * PCI-X Capability
  */
@@ -422,5 +530,6 @@
 	cap_pcix_stat_reg_t	pcix_type0_status;
 } cap_pcix_type0_t;
 
+#endif
 #endif	/* __ASSEMBLY__ */
 #endif /* _ASM_SN_PCI_PCI_DEFS_H */