patch-2.4.22 linux-2.4.22/arch/ppc/mm/4xx_mmu.c

• Lines: 38
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/ppc/mm/4xx_mmu.c
• Orig date: 2003-06-13 07:51:31.000000000 -0700

diff -urN linux-2.4.21/arch/ppc/mm/4xx_mmu.c linux-2.4.22/arch/ppc/mm/4xx_mmu.c
@@ -2,7 +2,7 @@
  * This file contains the routines for initializing the MMU
  * on the 4xx series of chips.
  *  -- paulus
- * 
+ *
  *  Derived from arch/ppc/mm/init.c:
  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  *
@@ -51,11 +51,6 @@
 #include <asm/machdep.h>
 #include <asm/setup.h>
 
-/* Used by the 4xx TLB replacement exception handler.
- * Just needed it declared someplace (and initialized to zero).
- */
-unsigned int tlb_4xx_index;
-
 /*
  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  */
@@ -89,7 +84,14 @@
 	 * Cache instruction and data space where the exception
 	 * vectors and the kernel live in real-mode.
 	 */
+	/*
+	 * Once the following code is enhanced to not assume that it should
+	 * just enable caching on the first 512MB, we need to make sure that
+	 * we either are given the cache in a known state or handle correctly
+	 * the cache being enabled previously.  Currently this will clear
+	 * without flushing. -- Tom
+	 */
 
-        mtspr(SPRN_DCCR, 0x80000000);	/* 128 MB of data space at 0x0. */
-        mtspr(SPRN_ICCR, 0x80000000);	/* 128 MB of instr. space at 0x0. */
+        mtspr(SPRN_DCCR, 0xF0000000);	/* 512 MB of data space at 0x0. */
+        mtspr(SPRN_ICCR, 0xF0000000);	/* 512 MB of instr. space at 0x0. */
 }