patch-2.4.22 linux-2.4.22/include/asm-mips64/pgtable.h

• Lines: 121
• Date: 2003-08-25 04:44:44.000000000 -0700
• Orig file: linux-2.4.21/include/asm-mips64/pgtable.h
• Orig date: 2002-11-28 15:53:15.000000000 -0800

diff -urN linux-2.4.21/include/asm-mips64/pgtable.h linux-2.4.22/include/asm-mips64/pgtable.h
@@ -16,87 +16,24 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/linkage.h>
+#include <asm/cacheflush.h>
 #include <linux/mmzone.h>
 #include <asm/cachectl.h>
 #include <asm/io.h>
 
-/* Cache flushing:
- *
- *  - flush_cache_all() flushes entire cache
- *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
- *  - flush_cache_page(mm, vmaddr) flushes a single page
- *  - flush_cache_range(mm, start, end) flushes a range of pages
- *  - flush_page_to_ram(page) write back kernel page to ram
- */
-extern void (*_flush_cache_all)(void);
-extern void (*___flush_cache_all)(void);
-extern void (*_flush_cache_mm)(struct mm_struct *mm);
-extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
-	unsigned long end);
-extern void (*_flush_cache_page)(struct vm_area_struct *vma,
-	unsigned long page);
-extern void (*_flush_page_to_ram)(struct page * page);
-extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
-extern void (*_flush_icache_page)(struct vm_area_struct *vma,
-	struct page *page);
-extern void (*_flush_cache_sigtramp)(unsigned long addr);
-extern void (*_flush_icache_all)(void);
-
-/* These suck ...  */
-extern void (*_flush_cache_l2)(void);
-extern void (*_flush_cache_l1)(void);
-
-
-#define flush_cache_all()		_flush_cache_all()
-#define __flush_cache_all()		___flush_cache_all()
-#define flush_dcache_page(page)		do { } while (0)
-
-#ifdef CONFIG_CPU_R10000
-/*
- * Since the r10k handles VCEs in hardware, most of the flush cache
- * routines are not needed. Only the icache on a processor is not
- * coherent with the dcache of the _same_ processor, so we must flush
- * the icache so that it does not contain stale contents of physical
- * memory. No flushes are needed for dma coherency, since the o200s
- * are io coherent. The only place where we might be overoptimizing
- * out icache flushes are from mprotect (when PROT_EXEC is added).
- */
-extern void andes_flush_icache_page(unsigned long);
-#define flush_cache_mm(mm)		do { } while(0)
-#define flush_cache_range(mm,start,end)	do { } while(0)
-#define flush_cache_page(vma,page)	do { } while(0)
-#define flush_page_to_ram(page)		do { } while(0)
-#define flush_icache_range(start, end)	_flush_cache_l1()
-#define flush_icache_user_range(vma, page, addr, len) \
-	flush_icache_page((vma), (page))
-#define flush_icache_page(vma, page)					\
-do {									\
-	if ((vma)->vm_flags & VM_EXEC)					\
-		andes_flush_icache_page(phys_to_virt(page_to_phys(page))); \
-} while (0)
+/*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty			PG_arch_1
 
-#else
+#define Page_dcache_dirty(page)		\
+	test_bit(PG_dcache_dirty, &(page)->flags)
+#define SetPageDcacheDirty(page)	\
+	set_bit(PG_dcache_dirty, &(page)->flags)
+#define ClearPageDcacheDirty(page)	\
+	clear_bit(PG_dcache_dirty, &(page)->flags)
 
-#define flush_cache_mm(mm)		_flush_cache_mm(mm)
-#define flush_cache_range(mm,start,end)	_flush_cache_range(mm,start,end)
-#define flush_cache_page(vma,page)	_flush_cache_page(vma, page)
-#define flush_page_to_ram(page)		_flush_page_to_ram(page)
-#define flush_icache_range(start, end)	_flush_icache_range(start, end)
-#define flush_icache_user_range(vma, page, addr, len) \
-	flush_icache_page((vma), (page))
-#define flush_icache_page(vma, page)	_flush_icache_page(vma, page)
-
-#endif /* !CONFIG_CPU_R10000 */
-
-#define flush_cache_sigtramp(addr)	_flush_cache_sigtramp(addr)
-#ifdef CONFIG_VTAG_ICACHE
-#define flush_icache_all()		_flush_icache_all()
-#else
-#define flush_icache_all()		do { } while(0)
-#endif
-
-#define flush_cache_l2()		_flush_cache_l2()
-#define flush_cache_l1()		_flush_cache_l1()
 
 /*
  * Each address space has 2 4K pages as its page directory, giving 1024
@@ -501,9 +438,17 @@
 extern pgd_t swapper_pg_dir[1024];
 extern void paging_init(void);
 
-extern void (*_update_mmu_cache)(struct vm_area_struct *vma,
-	unsigned long address, pte_t pte);
-#define update_mmu_cache(vma, address, pte) _update_mmu_cache(vma, address, pte)
+extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
+	pte_t pte);
+extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
+	pte_t pte);
+
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+	unsigned long address, pte_t pte)
+{
+	__update_tlb(vma, address, pte);
+	__update_cache(vma, address, pte);
+}
 
 /*
  * Non-present pages:  high 24 bits are offset, next 8 bits type,