patch-2.4.25 linux-2.4.25/arch/mips/au1000/common/pci_ops.c

• Lines: 213
• Date: 2004-02-18 05:36:30.000000000 -0800
• Orig file: linux-2.4.24/arch/mips/au1000/common/pci_ops.c
• Orig date: 2003-08-25 04:44:39.000000000 -0700

diff -urN linux-2.4.24/arch/mips/au1000/common/pci_ops.c linux-2.4.25/arch/mips/au1000/common/pci_ops.c
@@ -6,7 +6,8 @@
  * Author: MontaVista Software, Inc.
  *         	ppopov@mvista.com or source@mvista.com
  *
- *  Support for all devices (greater than 16) added by David Gathright.
+ *  - Support for all devices (greater than 16) added by David Gathright.
+ *  - Wired tlb fix for ioremap calls in interrupt routines by Embedded Edge.
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
@@ -36,6 +37,7 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/vmalloc.h>
 
 #include <asm/au1000.h>
 #ifdef CONFIG_MIPS_PB1000
@@ -53,6 +55,8 @@
 #define	DBG(x...)	
 #endif
 
+int (*board_pci_idsel)(unsigned int devsel, int assert);
+
 /* TBD */
 static struct resource pci_io_resource = {
 	"pci IO space", 
@@ -120,76 +124,154 @@
 
 #else
 
+
+/* CP0 hazard avoidance. */
+#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
+				     "nop; nop; nop; nop;\t" \
+				     ".set reorder\n\t")
+
+void mod_wired_entry(int entry, unsigned long entrylo0, 
+		unsigned long entrylo1, unsigned long entryhi, 
+		unsigned long pagemask)
+{
+	unsigned long old_pagemask;
+	unsigned long old_ctx;
+
+	/* Save old context and create impossible VPN2 value */
+	old_ctx = read_c0_entryhi() & 0xff;
+	old_pagemask = read_c0_pagemask();
+	write_c0_index(entry);
+	BARRIER;
+	write_c0_pagemask(pagemask);
+	write_c0_entryhi(entryhi);
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	BARRIER;
+	tlb_write_indexed();
+	BARRIER;
+	write_c0_entryhi(old_ctx);
+	BARRIER;
+	write_c0_pagemask(old_pagemask);
+}
+
+struct vm_struct *pci_cfg_vm;
+static int pci_cfg_wired_entry;
+static int first_cfg = 1;
+unsigned long last_entryLo0, last_entryLo1;
+
 static int config_access(unsigned char access_type, struct pci_dev *dev, 
 			 unsigned char where, u32 * data)
 {
-#ifdef CONFIG_SOC_AU1500
+#if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
 	unsigned char bus = dev->bus->number;
 	unsigned int dev_fn = dev->devfn;
 	unsigned int device = PCI_SLOT(dev_fn);
 	unsigned int function = PCI_FUNC(dev_fn);
-	unsigned long config, status;
-        unsigned long cfg_addr;
+	unsigned long offset, status;
+	unsigned long cfg_base;
+	unsigned long flags;
+	int error = PCIBIOS_SUCCESSFUL;
+	unsigned long entryLo0, entryLo1;
 
 	if (device > 19) {
 		*data = 0xffffffff;
 		return -1;
 	}
 
+	local_irq_save(flags);
 	au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)), 
 			Au1500_PCI_STATCMD);
-	//au_writel(au_readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG);
 	au_sync_udelay(1);
 
+	/*
+	 * We can't ioremap the entire pci config space because it's 
+	 * too large. Nor can we call ioremap dynamically because some 
+	 * device drivers use the pci config routines from within 
+	 * interrupt handlers and that becomes a problem in get_vm_area().
+	 * We use one wired tlb to handle all config accesses for all 
+	 * busses. To improve performance, if the current device
+	 * is the same as the last device accessed, we don't touch the
+	 * tlb.
+	 */
+	if (first_cfg) {
+		/* reserve a wired entry for pci config accesses */
+		first_cfg = 0;
+		pci_cfg_vm = get_vm_area(0x2000, 0);
+		if (!pci_cfg_vm) 
+			panic (KERN_ERR "PCI unable to get vm area\n");
+		pci_cfg_wired_entry = read_c0_wired();
+		add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, 
+				PM_4K);
+		last_entryLo0  = last_entryLo1 = 0xffffffff;
+	}
+
+	/* Since the Au1xxx doesn't do the idsel timing exactly to spec,
+	 * many board vendors implement their own off-chip idsel, so call
+	 * it now.  If it doesn't succeed, may as well bail out at this point.
+	 */
+	if (board_pci_idsel) {
+		if (board_pci_idsel(device, 1) == 0) {
+			*data = 0xffffffff;
+			local_irq_restore(flags);
+			return -1;
+		}
+	}
+
         /* setup the config window */
         if (bus == 0) {
-                cfg_addr = ioremap( Au1500_EXT_CFG | ((1<<device)<<11) , 
-				0x00100000);
+                cfg_base = ((1<<device)<<11);
         } else {
-                cfg_addr = ioremap( Au1500_EXT_CFG_TYPE1 | (bus<<16) | 
-				(device<<11), 0x00100000);
+                cfg_base = 0x80000000 | (bus<<16) | (device<<11);
         }
 
-        if (!cfg_addr)
-                panic (KERN_ERR "PCI unable to ioremap cfg space\n");
-
         /* setup the lower bits of the 36 bit address */
-        config = cfg_addr | (function << 8) | (where & ~0x3);
-
-#if 0
-	printk("cfg access: config %x, dev_fn %x, device %x function %x\n",
-			config, dev_fn, device, function);
-#endif
+        offset = (function << 8) | (where & ~0x3);
+	/* pick up any address that falls below the page mask */
+	offset |= cfg_base & ~PAGE_MASK;
+
+	/* page boundary */
+	cfg_base = cfg_base & PAGE_MASK;
+
+	entryLo0 = (6 << 26)  | (cfg_base >> 6) | (2 << 3) | 7;
+	entryLo1 = (6 << 26)  | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
+
+	if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
+		mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, 
+				(unsigned long)pci_cfg_vm->addr, PM_4K);
+		last_entryLo0 = entryLo0;
+		last_entryLo1 = entryLo1;
+	}
 
 	if (access_type == PCI_ACCESS_WRITE) {
-		au_writel(*data, config);
+		au_writel(*data, (int)(pci_cfg_vm->addr + offset));
 	} else {
-		*data = au_readl(config);
+		*data = au_readl((int)(pci_cfg_vm->addr + offset));
 	}
 	au_sync_udelay(2);
 
-
 	DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n", 
-			access_type, bus, device, where, *data, config);
-
-        /* unmap io space */
-        iounmap( cfg_addr );
+			access_type, bus, device, where, *data, offset);
 
 	/* check master abort */
 	status = au_readl(Au1500_PCI_STATCMD);
-#if 0
-printk("cfg access: status %x, data %x\n", status, *data );
-#endif
+
 	if (status & (1<<29)) { 
 		*data = 0xffffffff;
-		return -1;
+		error = -1;
 	} else if ((status >> 28) & 0xf) {
 		DBG("PCI ERR detected: status %x\n", status);
 		*data = 0xffffffff;
-		return -1;
-	} else {
-		return PCIBIOS_SUCCESSFUL;
+		error = -1;
+	} 
+	
+	/* Take away the idsel.
+	*/
+	if (board_pci_idsel) {
+		(void)board_pci_idsel(device, 0);
 	}
+
+	local_irq_restore(flags);
+	return error;
 #endif
 }
 #endif