patch-2.4.25 linux-2.4.25/arch/mips/au1000/common/power.c

• Lines: 300
• Date: 2004-02-18 05:36:30.000000000 -0800
• Orig file: linux-2.4.24/arch/mips/au1000/common/power.c
• Orig date: 2003-08-25 04:44:39.000000000 -0700

diff -urN linux-2.4.24/arch/mips/au1000/common/power.c linux-2.4.25/arch/mips/au1000/common/power.c
@@ -29,12 +29,11 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#include <linux/config.h>
+
 #include <linux/init.h>
 #include <linux/pm.h>
 #include <linux/slab.h>
 #include <linux/sysctl.h>
-#include <linux/acpi.h>
 
 #include <asm/string.h>
 #include <asm/uaccess.h>
@@ -49,13 +48,12 @@
 #  define DPRINTK(fmt, args...)
 #endif
 
-extern void au1k_wait(void);
 static void calibrate_delay(void);
 
-extern void set_au1000_speed(unsigned int new_freq);
-extern unsigned int get_au1000_speed(void);
-extern unsigned long get_au1000_uart_baud_base(void);
-extern void set_au1000_uart_baud_base(unsigned long new_baud_base);
+extern void set_au1x00_speed(unsigned int new_freq);
+extern unsigned int get_au1x00_speed(void);
+extern unsigned long get_au1x00_uart_baud_base(void);
+extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
 extern unsigned long save_local_and_disable(int controller);
 extern void restore_local_and_enable(int controller, unsigned long mask);
 extern void local_enable_irq(unsigned int irq_nr);
@@ -69,6 +67,141 @@
 
 static spinlock_t pm_lock = SPIN_LOCK_UNLOCKED;
 
+/* We need to save/restore a bunch of core registers that are
+ * either volatile or reset to some state across a processor sleep.
+ * If reading a register doesn't provide a proper result for a
+ * later restore, we have to provide a function for loading that
+ * register and save a copy.
+ *
+ * We only have to save/restore registers that aren't otherwise
+ * done as part of a driver pm_* function.
+ */
+static uint	sleep_aux_pll_cntrl;
+static uint	sleep_cpu_pll_cntrl;
+static uint	sleep_pin_function;
+static uint	sleep_uart0_inten;
+static uint	sleep_uart0_fifoctl;
+static uint	sleep_uart0_linectl;
+static uint	sleep_uart0_clkdiv;
+static uint	sleep_uart0_enable;
+static uint	sleep_usbhost_enable;
+static uint	sleep_usbdev_enable;
+static uint	sleep_static_memctlr[4][3];
+
+/* Define this to cause the value you write to /proc/sys/pm/sleep to
+ * set the TOY timer for the amount of time you want to sleep.
+ * This is done mainly for testing, but may be useful in other cases.
+ * The value is number of 32KHz ticks to sleep.
+ */
+#define SLEEP_TEST_TIMEOUT 1
+#ifdef SLEEP_TEST_TIMEOUT
+static	int	sleep_ticks;
+void wakeup_counter0_set(int ticks);
+#endif
+
+static void
+save_core_regs(void)
+{
+	extern void save_au1xxx_intctl(void);
+	extern void pm_eth0_shutdown(void);
+
+	/* Do the serial ports.....these really should be a pm_*
+	 * registered function by the driver......but of course the
+	 * standard serial driver doesn't understand our Au1xxx
+	 * unique registers.
+	 */
+	sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
+	sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
+	sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
+	sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
+	sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
+
+	/* Shutdown USB host/device.
+	*/
+	sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
+
+	/* There appears to be some undocumented reset register....
+	*/
+	au_writel(0, 0xb0100004); au_sync();
+	au_writel(0, USB_HOST_CONFIG); au_sync();
+
+	sleep_usbdev_enable = au_readl(USBD_ENABLE);
+	au_writel(0, USBD_ENABLE); au_sync();
+
+	/* Save interrupt controller state.
+	*/
+	save_au1xxx_intctl();
+
+	/* Clocks and PLLs.
+	*/
+	sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
+
+	/* We don't really need to do this one, but unless we
+	 * write it again it won't have a valid value if we
+	 * happen to read it.
+	 */
+	sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
+
+	sleep_pin_function = au_readl(SYS_PINFUNC);
+
+	/* Save the static memory controller configuration.
+	*/
+	sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
+	sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
+	sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
+	sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
+	sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
+	sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
+	sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
+	sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
+	sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
+	sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
+	sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
+	sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
+}
+
+static void
+restore_core_regs(void)
+{
+	extern void restore_au1xxx_intctl(void);
+	extern void wakeup_counter0_adjust(void);
+
+	au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync();
+	au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
+	au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
+
+	/* Restore the static memory controller configuration.
+	*/
+	au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
+	au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
+	au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
+	au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
+	au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
+	au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
+	au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
+	au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
+	au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
+	au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
+	au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
+	au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
+
+	/* Enable the UART if it was enabled before sleep.
+	 * I guess I should define module control bits........
+	 */
+	if (sleep_uart0_enable & 0x02) {
+		au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
+		au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
+		au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
+		au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
+		au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
+		au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
+		au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
+	}
+
+	restore_au1xxx_intctl();
+	wakeup_counter0_adjust();
+}
+
 unsigned long suspend_mode;
 
 void wakeup_from_suspend(void)
@@ -79,33 +212,48 @@
 int au_sleep(void)
 {
 	unsigned long wakeup, flags;
+	extern	void	save_and_sleep(void);
+
 	spin_lock_irqsave(&pm_lock,flags);
 
+	save_core_regs();
+
 	flush_cache_all();
-	/* pin 6 is gpio */
+
+	/** The code below is all system dependent and we should probably
+	 ** have a function call out of here to set this up.  You need
+	 ** to configure the GPIO or timer interrupts that will bring
+	 ** you out of sleep.
+	 ** For testing, the TOY counter wakeup is useful.
+	 **/
+
+#if 0
 	au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
 
 	/* gpio 6 can cause a wake up event */
 	wakeup = au_readl(SYS_WAKEMSK);
 	wakeup &= ~(1 << 8);	/* turn off match20 wakeup */
 	wakeup |= 1 << 6;	/* turn on gpio 6 wakeup   */
-	au_writel(wakeup, SYS_WAKEMSK);
-
+#else
+	/* For testing, allow match20 to wake us up.
+	*/
+#ifdef SLEEP_TEST_TIMEOUT
+	wakeup_counter0_set(sleep_ticks);
+#endif
+	wakeup = 1 << 8;	/* turn on match20 wakeup   */
+	wakeup = 0;
+#endif
 	au_writel(1, SYS_WAKESRC);	/* clear cause */
-	au_writel(1, SYS_SLPPWR);	/* prepare to sleep */
+	au_sync();
+	au_writel(wakeup, SYS_WAKEMSK);
+	au_sync();
 
-	__asm__("la $4, 1f\n\t"
-		"lui $5, 0xb190\n\t"
-		"ori $5, 0x18\n\t"
-		"sw $4, 0($5)\n\t"
-		"li $4, 1\n\t"
-		"lui $5, 0xb190\n\t"
-		"ori $5, 0x7c\n\t"
-		"sw $4, 0($5)\n\t" "sync\n\t" "1:\t\n\t" "nop\n\t");
+	save_and_sleep();
 
 	/* after a wakeup, the cpu vectors back to 0x1fc00000 so
 	 * it's up to the boot code to get us back here.
 	 */
+	restore_core_regs();
 	spin_unlock_irqrestore(&pm_lock, flags);
 	return 0;
 }
@@ -114,11 +262,27 @@
 		       void *buffer, size_t * len)
 {
 	int retval = 0;
+#ifdef SLEEP_TEST_TIMEOUT
+#define TMPBUFLEN2 16
+	char buf[TMPBUFLEN2], *p;
+#endif
 
 	if (!write) {
 		*len = 0;
 	} else {
+#ifdef SLEEP_TEST_TIMEOUT
+		if (*len > TMPBUFLEN2 - 1) {
+			return -EFAULT;
+		}
+		if (copy_from_user(buf, buffer, *len)) {
+			return -EFAULT;
+		}
+		buf[*len] = 0;
+		p = buf;
+		sleep_ticks = simple_strtoul(p, &p, 0);
+#endif
 		retval = pm_send_all(PM_SUSPEND, (void *) 2);
+
 		if (retval)
 			return retval;
 
@@ -132,6 +296,7 @@
 			 void *buffer, size_t * len)
 {
 	int retval = 0;
+	void	au1k_wait(void);
 
 	if (!write) {
 		*len = 0;
@@ -188,13 +353,13 @@
 			return -EFAULT;
 		}
 
-		old_baud_base = get_au1000_uart_baud_base();
-		old_cpu_freq = get_au1000_speed();
+		old_baud_base = get_au1x00_uart_baud_base();
+		old_cpu_freq = get_au1x00_speed();
 
 		new_cpu_freq = pll * 12 * 1000000;
 		new_baud_base = (new_cpu_freq / 4) / 16;
-		set_au1000_speed(new_cpu_freq);
-		set_au1000_uart_baud_base(new_baud_base);
+		set_au1x00_speed(new_cpu_freq);
+		set_au1x00_uart_baud_base(new_baud_base);
 
 		old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
 		new_refresh =
@@ -324,10 +489,4 @@
 			loops_per_jiffy &= ~loopbit;
 	}
 }
-
-void au1k_wait(void)
-{
-	__asm__("nop\n\t" "nop\n\t");
-}
-
 #endif				/* CONFIG_PM */