patch-2.4.3 linux/include/asm-sparc64/asi.h

• Lines: 80
• Date: Sun Mar 25 18:14:21 2001
• Orig file: v2.4.2/linux/include/asm-sparc64/asi.h
• Orig date: Fri Dec 13 01:37:41 1996

diff -u --recursive --new-file v2.4.2/linux/include/asm-sparc64/asi.h linux/include/asm-sparc64/asi.h
@@ -1,4 +1,4 @@
-/* $Id: asi.h,v 1.1 1996/11/20 12:59:45 davem Exp $ */
+/* $Id: asi.h,v 1.4 2001/03/15 02:08:46 davem Exp $ */
 #ifndef _SPARC64_ASI_H
 #define _SPARC64_ASI_H
 
@@ -23,19 +23,35 @@
 #define ASI_PNFL		0x8a /* Primary, no fault, little endian	*/
 #define ASI_SNFL		0x8b /* Secondary, no fault, little endian	*/
 
-/* SpitFire extended ASIs. */
+/* SpitFire and later extended ASIs.  The "(III)" marker designates
+ * UltraSparc-III specific ASIs.
+ */
 #define ASI_PHYS_USE_EC		0x14 /* PADDR, E-cachable			*/
-#define ASI_PHYS_BYPASS_EC_E	0x15 /* PADDR, E-cachable, E-bit		*/
+#define ASI_PHYS_BYPASS_EC_E	0x15 /* PADDR, E-bit				*/
 #define ASI_PHYS_USE_EC_L	0x1c /* PADDR, E-cachable, little endian	*/
-#define ASI_PHYS_BYPASS_EC_E_L	0x1d /* PADDR, E-cachable, E-bit, little endian	*/
+#define ASI_PHYS_BYPASS_EC_E_L	0x1d /* PADDR, E-bit, little endian		*/
 #define ASI_NUCLEUS_QUAD_LDD	0x24 /* Cachable, qword load			*/
 #define ASI_NUCLEUS_QUAD_LDD_L	0x2c /* Cachable, qword load, little endian 	*/
+#define ASI_PCACHE_DATA_STATUS	0x30 /* (III) PCache data status RAM diag	*/
+#define ASI_PCACHE_DATA		0x31 /* (III) PCache data RAM diag		*/
+#define ASI_PCACHE_TAG		0x32 /* (III) PCache tag RAM diag		*/
+#define ASI_PCACHE_SNOOP_TAG	0x33 /* (III) PCache snoop tag RAM diag		*/
+#define ASI_WCACHE_VALID_BITS	0x38 /* (III) WCache Valid Bits diag		*/
+#define ASI_WCACHE_DATA		0x39 /* (III) WCache data RAM diag		*/
+#define ASI_WCACHE_TAG		0x3a /* (III) WCache tag RAM diag		*/
+#define ASI_WCACHE_SNOOP_TAG	0x3b /* (III) WCache snoop tag RAM diag		*/
+#define ASI_DCACHE_INVALIDATE	0x42 /* (III) DCache Invalidate diag		*/
+#define ASI_DCACHE_UTAG		0x43 /* (III) DCache uTag diag			*/
+#define ASI_DCACHE_SNOOP_TAG	0x44 /* (III) DCache snoop tag RAM diag		*/
 #define ASI_LSU_CONTROL		0x45 /* Load-store control unit			*/
+#define ASI_DCU_CONTROL_REG	0x45 /* (III) DCache Unit Control Register	*/
 #define ASI_DCACHE_DATA		0x46 /* Data cache data-ram diag access		*/
 #define ASI_DCACHE_TAG		0x47 /* Data cache tag/valid ram diag access	*/
 #define ASI_INTR_DISPATCH_STAT	0x48 /* IRQ vector dispatch status		*/
 #define ASI_INTR_RECEIVE	0x49 /* IRQ vector receive status		*/
 #define ASI_UPA_CONFIG		0x4a /* UPA config space			*/
+#define ASI_SAFARI_CONFIG	0x4a /* (III) Safari Config Register		*/
+#define ASI_SAFARI_ADDRESS	0x4a /* (III) Safari Address Register		*/
 #define ASI_ESTATE_ERROR_EN	0x4b /* E-cache error enable space		*/
 #define ASI_AFSR		0x4c /* Async fault status register		*/
 #define ASI_AFAR		0x4d /* Async fault address register		*/
@@ -55,16 +71,23 @@
 #define ASI_DTLB_DATA_ACCESS	0x5d /* Data-MMU TLB data access register	*/
 #define ASI_DTLB_TAG_READ	0x5e /* Data-MMU TLB tag read register		*/
 #define ASI_DMMU_DEMAP		0x5f /* Data-MMU TLB demap			*/
+#define ASI_IIU_INST_TRAP	0x60 /* (III) Instruction Breakpoint register	*/
 #define ASI_IC_INSTR		0x66 /* Insn cache instrucion ram diag access	*/
 #define ASI_IC_TAG		0x67 /* Insn cache tag/valid ram diag access	*/
+#define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram diag	*/
 #define ASI_IC_PRE_DECODE	0x6e /* Insn cache pre-decode ram diag access	*/
 #define ASI_IC_NEXT_FIELD	0x6f /* Insn cache next-field ram diag access	*/
+#define ASI_BRPRED_ARRAY	0x6f /* (III) Branch Prediction RAM diag	*/
 #define ASI_BLK_AIUP		0x70 /* Primary, user, block load/store		*/
 #define ASI_BLK_AIUS		0x71 /* Secondary, user, block load/store	*/
+#define ASI_EC_DATA		0x74 /* (III) E-cache data staging register	*/
+#define ASI_EC_CTRL		0x75 /* (III) E-cache control register		*/
 #define ASI_EC_W		0x76 /* E-cache diag write access		*/
 #define ASI_UDB_ERROR_W		0x77 /* External UDB error registers write	*/
 #define ASI_UDB_CONTROL_W	0x77 /* External UDB control registers write	*/
-#define ASI_UDB_INTR_W		0x77 /* External UDB IRQ vector dispatch write	*/
+#define ASI_INTR_W		0x77 /* IRQ vector dispatch write		*/
+#define ASI_INTR_DATAN_W	0x77 /* (III) Outgoing irq vector data reg N	*/
+#define ASI_INTR_DISPATCH_W	0x77 /* (III) Interrupt vector dispatch		*/
 #define ASI_BLK_AIUPL		0x78 /* Primary, user, little, blk ld/st	*/
 #define ASI_BLK_AIUSL		0x79 /* Secondary, user, little, blk ld/st	*/
 #define ASI_EC_R		0x7e /* E-cache diag read access		*/
@@ -72,7 +95,8 @@
 #define ASI_UDBL_ERROR_R	0x7f /* External UDB error registers read low	*/
 #define ASI_UDBH_CONTROL_R	0x7f /* External UDB control registers read hi	*/
 #define ASI_UDBL_CONTROL_R	0x7f /* External UDB control registers read low	*/
-#define ASI_UDB_INTR_R		0x7f /* External UDB IRQ vector dispatch read	*/
+#define ASI_INTR_R		0x7f /* IRQ vector dispatch read		*/
+#define ASI_INTR_DATAN_R	0x7f /* (III) Incoming irq vector data reg N	*/
 #define ASI_PST8_P		0xc0 /* Primary, 8 8-bit, partial		*/
 #define ASI_PST8_S		0xc1 /* Secondary, 8 8-bit, partial		*/
 #define ASI_PST16_P		0xc2 /* Primary, 4 16-bit, partial		*/